Intel Changes CPU Road Map

Intel has announced several changes to its road map for server
processors, delaying its first dual-core Itanium 2 processor and
replacing a future multicore Xeon processor with a new design that
eliminates the performance penalty of shared connections to a chipset.

Montecito, the dual-core version of the Itanium 2 processor, will not
be available in large volumes until the middle of next year, instead
of the early part of next year as originally planned, said Scott
McLaughlin, an Intel spokesperson, on Monday. While preliminary
shipments of the processor are already under way, Intel decided to
make a few changes to the chip in order to reach the company's
standard for "production level quality," McLaughlin said, declining to
specify the nature of the changes.

But Montecito will no longer ship with Foxton, a sophisticated
power-management technology, and the speed of its front-side bus
connection to memory will run at 533MHz instead of the 667MHz speed
originally scheduled for the design, he said.

Chips Killed
Intel also has killed Whitefield, a multicore Xeon processor for
servers with four or more processors, McLaughlin said. It is being
replaced by a new processor code-named Tigerton that will appear in
2007, the same time-frame in which Whitefield was expected to arrive.

Tigerton processors will use a high-speed interconnect technology that
will allow each processor to connect directly to the server's chipset,
McLaughlin said. Current Xeon processors in multiprocessor servers
must share a front-side bus connection to the chipset in order to
access data from system memory or I/O, a bottleneck that industry
analysts have blamed for the current performance gap between Intel's
server chips and Advanced Micro Devices Inc.'s Opteron processors.

Intel's next-generation architecture, announced by President and Chief
Executive Officer Paul Otellini in August, will be used as the
blueprint for Tigerton. This architecture is based on low-power design
principles used to build Intel's Pentium M processor for notebooks.

Whitefield had been expected to help tip the performance battle back
toward Intel in 2007, but Tigerton should be even more powerful,
McLaughlin said. AMD has enjoyed favorable reviews from industry
analysts, and even companies such as Hewlett-Packard, for the
performance of its Opteron server processors as compared to Intel's
Xeon chips.

Intel is not specifying exactly how the Tigerton processors will
connect to the server's chipset, such as whether they will use
integrated memory or I/O controllers or a next-generation interconnect
technology that Intel has vaguely discussed at previous Intel
Developer Forums.

Socket Compatibility Sought
The Caneland platform, or the combination of Tigerton and its related
chipset, is not the design that will bring socket compatibility to
Intel's Xeon and Itanium processors, McLaughlin said. Intel wants to
make a chipset that can accommodate either a Xeon processor or an
Itanium processor, which will help reduce product development costs
for both Intel and its partners. That compatibility is slated to
arrive along with Tukwila, a multicore Itanium 2 processor now
scheduled to arrive in 2008 as a result of the Montecito delay, he
said. Intel is still evaluating when its Xeon processors will be
designed for that compatibility.

Intel had been expected to introduce an integrated memory controller
design at the same time it engineered the compatibility between
Itanium and Xeon, said Nathan Brookwood, principal analyst with
Insight 64 in Saratoga, California. Intel had never publicly confirmed
those plans, but the company has spoken in general terms about the
need for integrated memory controllers at some point in the future.

An integrated memory controller means the logic responsible for
coordinating the exchange of information between the processor and
memory is built right onto the processor, allowing it to run at the
same speed as the processor and improving overall system performance.
Since Intel would have had to make significant changes to its
processor and chipset designs in order to make the Xeon and Itanium
processors fit into the same chipset, it was considered a logical time
to introduce an integrated memory controller, he said.

Cache Changes to Come?
AMD's Opteron uses both point-to-point interconnects like Tigerton's
and an integrated memory controller. But Intel has been reluctant to
embrace integrated memory controllers, said Dean McCarron, principal
analyst with Mercury Research in Cave Creek, Arizona. Leaving the
memory controller on the chipset allows Intel to more easily
accommodate changes in memory standards, because it's much easier to
change a chipset design than a processor design, he said.

One reason for moving out the common architecture target date, and
therefore the potential integrated memory controller, could be that
Intel plans to increase the size of cache memory on its future
processors, McCarron said. Cache memory stores frequently used data
right next to the CPU where it can be accessed much more quickly than
data stored in the main memory chips.

The combination of larger cache memory and the direct connections
between Tigerton processors and chipsets could provide a significant
performance boost for Intel-based servers in 2007, McCarron said. It's
very early to know for sure, with even sample chips still far away, he
said.

However, Tigerton will certainly be more efficient than Whitefield
because of the new interconnect design, Brookwood said. "What happens
on the chip matters a lot, obviously, but ultimately the performance
of these chips is constrained by how fast you can feed them data," he
said.

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